It has been common in the field to use a so-called "0.3-GMSK" modulation scheme for wireless communication, where pre-modulated binary data is mapped to +1/-1 and held for a bit duration (T) and filtered with a Gaussian filter of normalized bandwidth (BT) equal to 0.3, where B is the actual bandwidth of the filter. This filtered signal is then FM modulated with modulation index of 0.5, which is the minimum for an FSK system and hence the term "Minimum Shift Keying (MSK)."
FIG. 1 illustrates a representative 0.3-GMSK system block diagram. On the transmitter side, a bi-polar signal is applied to a Gaussian filter 100, which is connected to a Minimum-Shift-Keying (MSK) 110 before the signal is transmitted to a receiver through an intermediate frequency (IF) to radio frequency (RF) converter 114 and an antenna 115. On the receiver side, the received signal from an antenna 120 goes through an RF-to-IF converter 121 to a bandpass filter 125 connected to a limiter 130, which limits the input signal amplitude. The signal from the limiter 130 is applied to an FM demodulator 140 before the signal is passed through a low-pass filter 150.
The resulting analog signal from the low-pass filter 150 is sampled by a sampler 155, through a sampling clock 156 and converted to digital form by an analog/digital (A/D) converter 160 for digital signal processing. The output of the A/D converter is applied to the detection device 170. However, due to intersymbol interference (ISI) intrinsically generated when the signal is filtered by the Gaussian filter 100 in the transmitter and typically introduced by the propagation channel, as well as the filters in the receiver. Therefore, it is desirable to be able to detect the baseband signal while minimizing the ISI impact at the output of the low-pass filter 150.
The FM-demodulated signal can be detected using fixed multi-threshold detection. However, with fixed multi-threshold detection, the accuracy of the decoded data tends to be sensitive to the corresponding phase offset. Therefore, additional mechanisms are needed to periodically adjust the sample time to ensure the correct phase for the detection scheme. These may include adjusting the sampler clock or using interpolation filters to re-generate the sampling phase. Note that the phase offset is determined by a digital processor, shown in block 230 and 330 of FIGS. 2 and 3, which estimates a sequence of previous samples.
FIGS. 2 and 3 illustrate fixed threshold detection circuits using an interpolation filter and using clock adjustment, respectively. However, as those skilled in the art will appreciate, both the interpolation filter and clock-adjustment would require a more complicated circuit. Therefore, It would be desirable to have a threshold detection circuit without the need to adjust the phases of input signals.
Referring to FIG. 2, the analog signal from the low-pass filter 150 in FIG. 1 is sampled by the sampler 210 according to a sampling clock 240 and quantized by an A/D converter 215. The resulted signal is applied to an interpolation filter 220 with the phase offset information produced by the digital processor 230. The output from the interpolation filter is applied to the detection circuit 250.
Referring to FIG. 3, where the method of clock adjustment is used, the analog signal is sampled by the sampler 310 according to the clock 340 and quantized by an A/D converter 315. Without the interpolation filter, the phase offset is applied to the sampling clock 340 from the digital processor 330.